Technical Field
The present invention relates to an organic light-emitting display device, and more particularly to an organic light-emitting display device that enables the realization of a high resolution.
Discussion of the Related Art
An image display device, which realizes various pieces of information on a screen, is a core technology of the information and communication age, and is being developed in the direction of becoming thinner, lighter, more portable, and having higher performance. As one example of a flat panel display device that is capable of overcoming the problems of disadvantageous weight and volume of a cathode ray tube (CRT), an organic light-emitting display (OLED) device, which displays an image by controlling the intensity of luminescence of an organic emission layer, is attracting attention. The OLED device is a self-illuminating device and is characterized by low power consumption, high response speed, high luminance efficacy, high brightness, and a wide viewing angle.
The OLED device displays an image using a plurality of subpixels, which are arranged in a matrix form. Here, each subpixel includes a light-emitting diode and a pixel-driving circuit having multiple transistors that implement independent driving of the light-emitting diode.
The light-emitting diode is formed on the multiple transistors included in the pixel-driving circuit through a mask process separately from the multiple transistors. Accordingly, as shown in FIG. 1, an emission area EA, in which the light-emitting diode is disposed, overlaps a transistor area TA, in which the multiple transistors are disposed, in the vertical direction. However, a storage capacitor included in the pixel-driving circuit is formed in the same plane and through the same mask process as the multiple transistors. Accordingly, a capacitor area CA, in which the storage capacitor is disposed, does not overlap the transistor area TA and is spaced apart from the transistor area TA in the horizontal direction. Further, signal lines electrically connected to the multiple transistors, for example, a data line DL, a high-voltage VDD supply line VL1 and a low-voltage VSS supply line VL2, are arranged to be spaced apart from each other in the horizontal direction in consideration of the effect of parasitic capacitance. As such, because the signal lines DL, VL1 and VL2, the transistor area TA and the capacitor area CA are arranged on the substrate to be spaced apart from each other in the horizontal direction, a process margin is small, which makes it difficult to realize a high resolution and reduces production yield.